其中(1)腳為鎖存端,
(2)腳為串行數據輸入端,
(3)腳為串行時鐘端。(1)腳為高電平時,8位并行輸出口Q1~Q8在時鐘的上升沿隨串行輸入而變化;(1)腳為低電平時,輸出鎖定。利用鎖存端可方便地進行片選和級聯輸出控制。
(15)腳為并行輸出狀態控制端,(15)腳為低電平時,并行輸出端處在高阻狀態,在用CD4094作顯示輸出時,可使顯示數碼閃爍。(
9)腳QS、(10)腳Q′S是串行數據輸出端,用于級聯。QS端在第9個串行時鐘的上升沿開始輸出,Q′S端在第9個串行時鐘的下降沿開始輸出。
當CD4094電源為5V時,輸出電流大于3.2MA,灌電流為1 MA。串行時鐘頻率可達2.5MHZ。
CD4094引腳圖
CD4094真值表:
Clock
| Output Enable
| Strobe
| Data
| Parallel Outputs 并行輸出
| Serial Outputs 串行輸出
| ||
Q1
| QN
| QS (Note 1)
| Q S
| ||||
↑
| 0
| X
| X
| 三態
| 三態
| Q7
| 不變
|
↓
| 0
| X
| X
| 三態
| 三態
| 不變
| Q7
|
↑
| 1
| 0
| X
| 不變
| 不變
| Q7
| 不變
|
↑
| 1
| 1
| 0
| 0
| QN-1
| Q7
| 不變
|
↑
| 1
| 1
| 1
| 1
| QN-1
| Q7
| 不變
|
↓
| 1
| 1
| 1
| 不變
| 不變
| 不變
| Q7
|
CD4094內部電路方框圖
Absolute Maximum Ratings 絕對最大額定值:
Supply Voltage電源電壓(VDD)
| -0.5 to +18 VDC
|
Input Voltage輸入電壓 (VIN)
| -0.5 to VDD +0.5 VDC
|
Storage Temperature Range儲存溫度范圍 (TS)
| -65℃ to +150℃
|
Power Dissipation功耗 (PD)
| |
Dual-In-Line 普通雙列封裝
| 700 mW
|
Small Outline 小外形封裝
| 500 mW
|
Lead Temperature 焊接溫度(TL)
| |
Soldering, 10 seconds)(焊接10秒)
| 260℃
|
DC Supply Voltage 直流供電電壓 (VDD)
| +3.0 to +15 VDC
|
Input Voltage輸入電壓 (VIN)
| 0 to VDD VDC
|
Operating Temperature Range工作溫度范圍 (TA)
| -40℃ to +85℃
|
Symbol符號
| Parameter參數
| Conditions 條件
| -40°C
| +25°C
| +85°C
| Units 單位
| |||||
最小
| 最大
| 最小
| 典型
| 最大
| 最小
| 最大
| |||||
IDD
| Quiescent Device Current靜態電流
| VDD = 5.0V
|
| 20
|
|
| 20
|
| 150
| μA
| |
VDD = 10V
|
| 40
|
|
| 40
|
| 300
| ||||
VDD = 15V
|
| 80
|
|
| 80
|
| 600
| ||||
VOL
| LOW Level Output Voltage 輸出低電平電壓
| VDD=5.0V
| |IO|≤1.μA
|
| 0.05
|
| 0
| 0.05
|
| 0.05
| V
|
VDD=10V
|
| 0.05
|
| 0
| 0.05
|
| 0.05
| ||||
VDD=15V
|
| 0.05
|
| 0
| 0.05
|
| 0.05
| ||||
VOH
| HIGH Level Output Voltage 輸出高電平電壓
| VDD=5.0V
| |IO|≤1μA
| 4.95
|
| 4.95
| 5.0
|
| 4.95
|
| V
|
VDD=10V
| 9.95
|
| 9.95
| 10.0
|
| 9.95
|
| ||||
VDD=15V
| 14.95
|
| 14.95
| 15.0
|
| 14.95
|
| ||||
VIL
| LOW Level Input Voltage 輸入低電平電壓
| VDD = 5.0V, VO = 0.5V or 4.5V
|
| 1.5
|
|
| 1.5
|
| 1.5
| V
| |
VDD = 10V, VO = 1.0V or 9.0V
|
| 3.0
|
|
| 3.0
|
| 3.0
| ||||
VDD = 15V, VO = 1.5V or 13.5V
|
| 4.0
|
|
| 4.0
|
| 4.0
| ||||
VIH
| HIGH Level Input Voltage 輸入高電平電壓
| VDD = 5.0V, VO = 0.5V or 4.5V
| 3.5
|
| 3.5
|
|
| 3.5
|
| V
| |
VDD = 10V, VO = 1.0V or 9.0V
| 7.0
|
| 7.0
|
|
| 7.0
|
| ||||
VDD = 15V, VO = 1.5V or 13.5V
| 11.0
|
| 11.0
|
|
| 11.0
|
| ||||
IOL
| LOW Level Output Current 輸出低電平電流 (Note 4)
| VDD=5.0V,VO=0.4V
| 0.52
|
| 0.44
| 0.88
|
| 0.36
|
| mA
| |
VDD=10V,VO=0.5V
| 1.3
|
| 1.1
| 2.25
|
| 0.9
|
| ||||
VDD=15V,VO=1.5V
| 3.6
|
| 3.0
| 8.8
|
| 2.4
|
| ||||
IOH
| HIGH Level Output Current 輸出高電平電流 (Note 4)
| VDD=5.0V,VO =4.6V
| -0.52
|
| -0.44
| 0.88
|
| -0.36
|
| mA
| |
VDD =10V,VO= 9.5V
| -1.3
|
| -1.1
| 2.25
|
| -0.9
|
| ||||
VDD=15V,VO =13.5V
| -3.6
|
| -3.0
| 8.8
|
| -2.4
|
| ||||
IIN
| Input Current 輸入電流
| VDD =15V,VIN =0V
|
| -0.3
|
|
| -0.3
|
| -1.0
| μA
| |
VDD=15V,VIN =15V
|
| 0.3
|
|
| 0.3
|
| 1.0
| ||||
IOZ
| 3-STATE Output Leakage Current 3態輸出漏電流
| VDD=15V,VIN=0V or 15V
|
| 1
|
|
| 1
|
| 10
| μA
|
Symbol 符號
| Parameter 參數
| Conditions 條件
| 最小
| 典型
| 最大
| Units 單位
|
tPHL, tPLH
| Propagation Delay Clock to QS
| VDD = 5.0V
|
| 300
| 600
| ns
|
VDD = 10V
|
| 125
| 250
| |||
VDD = 15V
|
| 95
| 190
| |||
tPHL, tPLH
| Propagation Delay Clock to Q¢ S
| VDD = 5.0V
|
| 230
| 460
| ns
|
VDD = 10V
|
| 110
| 220
| |||
VDD = 15V
|
| 75
| 150
| ns
| ||
tPHL, tPLH
| Propagation Delay Clock to Parallel Out
| VDD = 5.0V
|
| 420
| 840
| ns
|
VDD = 10V
|
| 195
| 390
| |||
VDD = 15V
|
| 135
| 270
| |||
tPHL, tPLH
| Propagation Delay Strobe to Parallel Out
| VDD = 5.0V
|
| 290
| 580
| ns
|
VDD = 10V
|
| 145
| 290
| |||
VDD = 15V
|
| 100
| 200
| |||
tPHZ
| Propagation Delay HIGH Level to HIGH Impedance
| VDD = 5.0V
|
| 140
| 280
| ns
|
VDD = 10V
|
| 75
| 150
| |||
VDD = 15V
|
| 55
| 110
| |||
tPLZ
| Propagation Delay LOW Level to HIGH Impedance
| VDD = 5.0V
|
| 140
| 280
| ns
|
VDD = 10V
|
| 75
| 150
| |||
VDD = 15V
|
| 55
| 110
| |||
tPZH
| Propagation Delay HIGH Impedance to HIGH Level
| VDD = 5.0V
|
| 140
| 280
| ns
|
VDD = 10V
|
| 75
| 150
| |||
VDD = 15V
|
| 55
| 110
| |||
tPZL
| Propagation Delay HIGH Impedance to LOW Level
| VDD = 5.0V
|
| 140
| 280
| ns
|
VDD = 10V
|
| 75
| 150
| |||
VDD = 15V
|
| 55
| 110
| |||
tTHL, tTLH
| Transition Time過渡時間
| VDD = 5.0V
|
| 100
| 200
| ns
|
VDD = 10V
|
| 50
| 100
| |||
VDD = 15V
|
| 40
| 80
| |||
tSU
| Set-Up Time Data to Clock 建立時間數據時鐘
| VDD = 5.0V
| 80
| 40
|
| ns
|
VDD = 10V
| 40
| 20
|
| |||
VDD = 15V
| 20
| 10
|
| |||
tr, tf
| Maximum Clock Rise and Fall Time最大時鐘上升和下降時間
| VDD = 5.0V
| 1
|
|
| ms
|
VDD = 10V
| 1
|
|
| |||
VDD = 15V
| 1
|
|
| |||
tPC
| Minimum Clock Pulse Width最小時鐘脈沖寬度
| VDD = 5.0V
| 200
| 100
|
| ns
|
VDD = 10V
| 100
| 50
|
| |||
VDD = 15V
| 83
| 40
|
| |||
tPS
| Minimum Strobe Pulse Width
| VDD = 5.0V
| 200
| 100
|
| ns
|
VDD = 10V
| 80
| 40
|
| |||
VDD = 15V
| 70
| 35
|
| |||
fmax
| Maximum Clock Frequency 最大時鐘頻率
| VDD = 5.0V
| 1.5
| 3.0
|
| MHz
|
VDD = 10V
| 3.0
| 6.0
|
| |||
VDD = 15V
| 4.0
| 8.0
|
| |||
CIN
| Input Capacitance 輸入電容
| Any Input
|
| 5.0
| 7.5
| pF
|
測試電路和3態時序圖
時序圖